ARM Assembly

From assembly to machine code

Directly on the ARM machine
Assemble the human-readable assembly code into an object file (program.o).
Link the object file into a fully executable program:
Resolves symbol references
Assigns final memory addresses
Adds startup code (if specified)
Produces an executable binary (program)
Not on the ARM machine
Assembly basics
ARM modes
ARM mode: 4 bytes (32-bit) instruction
Thumb mode: 2 bytes (16-bit) instruction
ARM datatypes

ARM Operation modes

Mode
Privileged
Purpose
User
No
Normal operating mode for most programs (tasks)
Fast Interrupt (FIQ)
Yes
Used to handle a high-priority (fast) interrupt
Interrupt (IRQ)
Yes
Used to handle a low-priority (normal) interrupt
Supervisor
Yes
Used when the processor is reset, and to handle the software interrupt instruction (SWI)
Abort
Yes
Used to handle memory access violations
Undefined
Yes
Used to handle undefined or unimplemented instructions
System
Yes
Uses the same registers as User mode
Registers use

CPSR

Flag
Description
N
Enabled if result of the instruction yields a negative number.
Z
Enabled if result of the instruction yields a zero value.
C
Enabled if result of the instruction yields a value that requires a 33rd bit to be fully represented.
V
Enabled if result of the instruction yields a value that cannot be represented in 32 bit two’s complement.
E
ARM can operate either in little endian, or big endian. This bit is set to 0 for little endian, or 1 for big endian
T
This bit is set if you are in Thumb state and is disabled when you are in ARM state.
M
These bits specify the current privilege mode (USR, SVC, etc.).
J
Third execution state that allows some ARM processors to execute Java bytecode in hardware.
Relationship between ARM and Intel processors

Instructions
MOV
Move data
MOV R0, R1
R0 = R1
MVN
Move and negate (bitwise NOT)
MVN R0, R1
R0 = ~R1
ADD
Addition
ADD R0, R1, R2
R0 = R1 + R2
SUB
Subtraction
SUB R0, R1, #5
R0 = R1 − 5
MUL
Multiplication
MUL R0, R1, R2
R0 = R1 × R2
LSL
Logical Shift Left
LSL R0, R1, #1
R0 = R1 << 1
LSR
Logical Shift Right
LSR R0, R1, #2
Shift right, fill with 0
ASR
Arithmetic Shift Right
ASR R0, R1, #1
Preserve sign
ROR
Rotate Right
ROR R0, R1, #4
Rotate bits right
CMP
Compare (sets flags)
CMP R0, #10
Compare R0 with 10
AND
Bitwise AND
AND R0, R1, R2
R0 = R1 & R2
ORR
Bitwise OR
ORR R0, R1, R2
R0 = R1 | R2
EOR
Bitwise XOR
EOR R0, R1, R2
R0 = R1 ^ R2
LDR
Load from memory
LDR R0, [R1]
R0 = *R1
STR
Store to memory
STR R0, [R1]
*R1 = R0
LDM
Load Multiple
LDMIA R0!, {R1-R3}
STM
Store Multiple
STMDB R0!, {R1-R3}
PUSH
Push on stack
PUSH {R0, R1}
POP
Pop off stack
POP {R0, R1}
B
Branch
B loop
BL
Branch with Link (function call)
BL myFunction
BX
Branch and eXchange
BX LR
Return from function
BLX
Branch with Link and eXchange
BLX R3
SWI / SVC
System call
SVC #0

Assembly sections
.text
Code
.data
Initialized variables
.bss
Uninitialized variables
.rodata
Constants
.init / .fini
Startup / shutdown
.symtab
Symbols
.debug_*
Debugging
.ARM.exidx
ARM exceptions
.got / .plt
Dynamic linking
Common Assembly snippets
Hello World
Further details
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